| S.No | Title | Page No | Download |
| IJIT 325 | A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits Authors:Y. HARI KRISHNA, G. SUNEEL KUMAR |
1648-1652 |
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| IJIT 326 | A New Cascaded Multilevel Inverter with Reduced Number of Switches for Photovoltaic Applications Authors:GANGIREDDY SRUJANA, K. RAMA MOHAN REDDY, M. REDDY PRASANNA |
1653-1660 |
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| IJIT 327 | Delay Efficient Carry Select Adder using Kogge Stone Approach Authors:DEVARAPALLI RAJESH, T. V. SRINIVASA RAO |
1661-1664 |
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| IJIT 328 | Area Efficient Implementation of MDC FFT Architecture Authors:M. SWARNA LATHA, K. HARI KRISHNA |
1665-1668 |
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| IJIT 329 | Area and Delay Efficient Shift Register using the Non-Overlapped Delayed Clock Pulses Authors:GERA DHARMENDRA KUMAR, DIVYA JONNALAGADDA |
1669-1672 |
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